Electrostatic discharge (ESD) phenomena commonly result from pulses of high voltage (typically, several kilovolts), moderate current (a few amperes) and short duration (on the order of 100 nanoseconds) generated by a variety of sources such as human bodies, electric fields generated by machinery, and the like. Several analytical models have been developed to approximate these phenomena, including: 1) the Human Body Model (described in more detail in MIL-STD 883C method 3015.7, hereby incorporated by reference), which is typical of ESD resulting from the movement of a human body during, e.g., handling of the device; 2) the Machine Model, which characterizes ESD resulting from charges developed in automated assembly areas; and 3) the Charged Device Model, which approximates ESD from manufacturing and handling devices.
ESD effects are a common problem in integrated circuit (IC) electronics and are particularly troublesome in complimentary metal oxide semiconductor (CMOS) devices which have particularly thin gate oxides and very short channel devices. Such structures typically can withstand only a few tens of volts, but is decreasing as CMOS processes become smaller. An ESD pulse conducted through a CMOS IC can induce oxide rupture and device or interconnect burnout, and have potentially disastrous consequences.
ESD problems can be minimized by including appropriate anti-static protection on the circuit boards on which the ICs are installed; however, the ICs still are susceptible to ESD before and during the circuit board fabrication process. A general personnel awareness of ESD problems and countermeasures such as electrically grounded bracelets and the like can minimize risks in this phase of the IC life span; however, it is at best a partial solution. Therefore, it is desirable to include ESD protection circuitry within the IC itself.
Diodes have been used to shunt the ESD current to ground. This approach has its drawbacks, however, since such diodes typically have a significant parasitic series resistance which limits the amount of Current that may be shunted. Furthermore, the forward current increases with temperature due to the increased saturation current and due to the reduced semiconductor band gap. Thus, heating that results from an ESD event further limits current carrying capability. Large area diodes may be used to reduce this resistance; however, this variation reduces the chip density and increases the input circuit's capacitance.
One such used of diodes is illustrated in FIG. 8, which shows an input cell 805. Diodes 800 and 810 are coupled to a node 815. Node 815 is coupled to in input pad 820 and an inverter or buffer 830. An output of inverter 830 is coupled to circuitry of an integrated circuit (not shown) via a lead 840. Diode 800 and inverter 830 are coupled to a power supply (not shown) via a lead 850 to receive V.sub.DD. Diode 800 is typically a PMOS transistor configured as a diode and diode 810 is typically a NMOS transistor configured as a diode.
When an input signal that is greater than V.sub.DD is provided to pad 820, diode 800 is forward biased and conducts to lead 850. Thus, the input signal is prevented from being propagated to the circuitry of the integrated circuit that is coupled to inverter 830.
For most ESD protection schemes, the trigger voltage of the protection device is lower than the break down voltage of the internal circuitry of an integrated circuit. However, these schemes may not work for applications with high input voltages. The high input voltages can be clipped by the ESD protection schemes that, for example, use a parasitic PN diode from input to V.sub.DD and a parasitic NP diode from input to ground.
A need exists for an ESD protection configuration that will allow high input signal voltages while shunting ESD voltages. The present invention meets this need.